Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing

SAU, CARLO;PALUMBO, FRANCESCA;MELONI, PAOLO;RAFFO, LUIGI
2017

Abstract

Applicable in different fields and markets, low energy high efficiency video coding (HEVC) codecs and their constituting elements have been heavily studied. Fractional pixel interpolation is one of its most costly blocks. In this letter, a field programmable gate array implementation of HEVC fractional pixel interpolation, outperforming literature solutions, is proposed. Approximate computing, in conjunction with hardware reconfiguration, guarantees a tunable interpolation system offering an energy versus quality tradeoff to further reduce energy.
Inglese
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http://www.ieee.org
http://ieeexplore.ieee.org/document/7932478/
Comitato scientifico
internazionale
scientifica
Embedded applications; field programmable gate array (FPGA); FIR filters; low power architectures; low power design; reconfigurable computing; runtime reconfiguration; signal processing; Control and Systems Engineering; Computer Science (all)
Sau, Carlo; Palumbo, Francesca; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, Paolo; Raffo, Luigi
1.1 Articolo in rivista
info:eu-repo/semantics/article
1 Contributo su Rivista::1.1 Articolo in rivista
262
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open
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