Dipartimento di Ingegneria elettrica ed elettronica

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  • Previous Master Thesis co-advising
    Marco Buttu: Design Of Low Power Dissipation Network On Chip Architectures
    Roberto Argiolas: Area and power modeling metodologies for Network-on-chip components
    with layout awareness
    Felice Melis: Power modeling metodologies for Network-on-chip components
    Murru Ernesto: Area modeling metodologies for Network-on-chip components
    Giuseppe Tuveri: FPGA based prototyping platform for NoC based multicore architectures
    Enrico Usai: FPGA based prototyping platform for bus-based multicore architectures
    Emanuele Luzzu: Configuration and behavioral simulation of the S1 core processor and
    architectural evaluation of the SUN OpenSPARC T1 architecture
    Nicola Carta: Implementation and evaluation of GALS communication techniques for on-chip
    networking.
    Massimo Camplani: Technologies for router optimization in Networks on Chip

 

  • Previous Master Theses co-advised in cooperation with foreign institutions:
    Sebastiano Pomata: Development of a cycle-accurate simulation infrastructure for memory
    hierarchies in multi-core systems (managed in cooperation with Barcelona Supercomputing
    Center)
    Gianluca Loi: Development and thermal-aware analysis of a memory-processor system in 3D
    ICs technology (managed in cooperation with University of Santa Barbara)

To be updated…

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