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Professor
GIOVANNI MARTINES (Tit.)
Period
Second Semester 
Teaching style
Teledidattica 
Lingua Insegnamento
ITALIANO 



Informazioni aggiuntive

Course Curriculum CFU Length(h)
[70/89]  ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING [89/46 - Ord. 2016]  ELETTRICA ON LINE E IN PRESENZA (BLENDED) 10 60
[70/89]  ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING [89/56 - Ord. 2016]  ELETTRONICA ON LINE E IN PRESENZA (BLENDED) 10 60
[70/89]  ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING [89/66 - Ord. 2016]  INFORMATICA ON LINE E IN PRESENZA (BLENDED) 10 60

Objectives

By the end of this course, the students should be able:

[Knowledge and understanding]
-to gain some knowledge of the working principle of solid state electronic devices;
-to learn and analyze the behavior of electronic amplifiers;
-to be familiar with the electronic amplifiers made with solid state devices even in the integrated circuits.
-to understand how CMOS logic gates work.

[Applied knowledge and understanding]
-to choose between equivalent models and between complexity analysis methodologies suitable to accomplish with the level of approximation required by the context;
-to determine the performance of amplifiers realized with solid state devices;
-to analyze the the way in which cascaded amplifier works also in integrated circuits;
-to study the behavior and the performance of the electronic amplifiers with negative feedback.

[Making judgments]
-to assess the applicability of methods for the simplification of the electronic circuits analysis;
-to compare the performance from different electronic systems;

[Communication skills]
-to present and discuss the strengths and weaknesses of a low-complexity electronic system;

[Learning abilities]
-to consult the literature and gather additional data to understand the issues related to the technical progress of a low-complexity electronic circuit.

Prerequisites

The compulsory prerequisites are indicated in the Degree Course's didactic regulations.
It is helpful to know the Fourier transform, the atom structure, the periodic system of the elements and the kinetic theory of gases. Also it is necessary to be able:
-to analyze electrical circuits with two or more meshes at the steady or sinusoidal state, determining the expressions of node voltages and branch currents also when controlled generators are present;
-to use the principles for characterizing networks, like dipole or double dipole;
-to recognize and to draw equivalent electrical networks;
-to analyze input-output models of a physical systems in the time domain, in the Laplace's variable domain and in the frequency domain;
-to draw the Bode plot of transfer functions;
-to appreciate the stability of linear systems;
-to use spreadsheet and programs for numerical simulation.

Contents

General information on amplifiers (5,5E-3I) Specification and performance of electronic systems. Energy balance. Standardization, terminology and standards for the technical drawing. Approximate representations and constructive tolerance. Equivalent circuit models and two-port parameters. Signals and frequency spectrum. Distortion. Analysis of cascaded amplifiers. Classification in the time and frequency domain. Unidirectional models. Saturation, biasing and linear approximation. Noise and related analysis methodologies. Cascaded stages interaction.
Pn junction diode (5,6E-2I). Basic semiconductor concepts. PN junction. Drift and diffusion currents. Current equation, vi characteristic, breakdown. Junction and diffusion capacitance. Diode models. SPICE models. Static and dynamic load line, operating point. Small-signal model. Power limits, the heat transfer model. Rectifiers and peak detectors, clamping and coupling circuits, limiters. Waveform shaper.
MOS transistor (8,0E-3I) Device structure, inversion layer and threshold voltage. Enhancement-mode N-channel MOSFET: operation regions, current equation, vi characteristics and transfer function, channel length modulation, body effect. P channel MOSFET. Depletion mode. CMOS technology. MOSFET in common source configuration (CS) as elementary amplifier: operation limits, load line, signal performance and the working point choice. Small signal operation and model. Bias network and the working point stability. Design criteria. Non-inverting amplifier (CG). Voltage follower (CD). Performance comparisons. Frequency response and methodologies OCTC and SCTC.
Fully integrated CMOS amplifiers (7,0E-2I). Current mirror circuit. Wilson, Widlar and cascode current source. Performance comparisons, merit figures. CS stage with active load. MOS Differential pair: large-signal operation, operating limits, linear operating region. Design equations, equivalent circuits. Cascode CMOS differential pairs. CMRR and frequency response.
Output stages (2,3E-2I). Design specification, performance, classification. Realization and project examples of stages in class A, B and AB. Protection circuits.
Operational Amplifiers (4,8E-3I). Characteristics. Closed loop operation. Inverting and non-inverting amplifier. Non-ideal effects: gain, bandwidth, input and output impedance, CMRR, slew rate, offsets, stability, power. Other applications: adder, differential amplifier, iv converter, integrator, differentiator.
Theory of feedback amplifiers (2,8E-2I). Basic topologies, ideal and practical situations, analysis methodologies, performance comparison.
Bipolar Junction Transistor (3,3E-2I). Sructure of an NPN transistor, current flows, concentrations of minority carriers, currents equations. Early effect. Graphic representations of the transistor characteristics. T and Pi-greek models, Ebers-Moll model. Epitaxial technology., PNP transistor. Small-signal model. BJT biasing. Single stage BJT amplifiers: CE, CB, CC. Design equations, performance comparisons. Thyristor, triac, diac with application examples.
CMOS logic gates circuits (2,8E-1I). Inverter: VTC, signal levels, noise immunity. CMOS inverter. Logic gate performance, energy-delay and power-delay product. Pull-up networks. Pull-down networks. Hierarchical classification, logic gate symbols and truth tables. NOR gate. NAND gate. Methods in synthesis of PUN and PDN.

Teaching Methods

The course is available in e-learning: about two thirds as educational teaching (40 hours E), i.e. as a set of pre-packaged blocks, available and traceable in a dedicated e-learning platform; each block consists of video lessons and textual material; the remaining third (20 hours I) are activities involving the interaction of the student with the teacher or the virtual class tutor, using tools such as email, forums and virtual classroom / videoconferencing.
The course is divided into 9 modules for a total of 31 lessons, in turn divided into teaching units lasting about 20 minutes each. Each teaching unit is organized functionally to the specific educational goal and is formed by the recording of the lesson with the support of slides and textual material.

Verification of learning

In order to allow students to self-evaluate their knowledge, and instructor to monitor students comprehension, during the lectures, one anonymous test is given to the students in a multiple choice format and correct answers are showed at the end. During the period provided for by the academic calendar, two intermediate tests are done, which are developed with the same rules of final written examinations, the only difference is that each intermediate test concerns only half of the course program. These tests are corrected and marked by the instructor. The two intermediate tests can replace the written end-of-course exam.

The final exam consists of a written test and in a optional oral test. It is possible to take the oral test also in case of insufficient the mark of the written test. The written test consists in analyzing a medium complexity electronic circuit through the basic circuit recognition and the implementation of the electronic methodologies. The test lasts 2 hours, students are allowed to use a calculator and a reference book can be consulted during the written test, same rules apply to the slides showed during lectures. The oral test is based on the discussion of the written test and on the exposition of one topic covered in the course.
The written test aims at evaluating the achievement of the educational objectives, and in particular:
-ability to pick out the known circuits in a limited complexity diagram;
-ability to choose the analysis methodology suitable for the level of approximation required;
-ability to work out the analysis of a medium complexity circuit starting from the wiring diagram.
The oral test evaluates the specific skills acquired by the student about the comprehension and the analysis of the electronic circuits and the ability to evaluate the solutions adopted and identify the causes of unexpected behaviors.
The mark assigned at the written part is based on an evaluation table connected to the questions specifically asked to the student. The highest mark for the written part is 28/30.
The final mark after the optional oral part is assigned on the base of the reassessment of the written part resulting from the discussion with the student and by the evaluation of the exposition of the topic asked, and the specific knowledge together with the correct use of technical language.

To meet needs arising from the epidemiological situation, the intermediate written tests can be eliminated and the written test of the final exam can be replaced by oral interviews.

Texts

Adel Sedra, Kenneth Smith: "Microelectronic circuits", Oxford University Press .
- Richard C. Jaeger, Travis N. Blalock “Microelectronic Circuit Design, Third Edition”, McGraw-Hill, New York.

The texts are equivalent for studying and are recommended also delve into topics not covered by the course.

More Information

The video lessons are accessible on the network asynchronously using the most common media (PC, smart phone, tablet) and the most common INTERNET browsers (Explorer, Crome, Mozilla, etc.).
It is also possible download to multimedia support, for use off-line, some specific content such as slides, charts, exercises suggested and exercises carried out.

Questionnaire and social

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