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Professor
LUIGI RAFFO (Tit.)
Period
First Semester 
Teaching style
Convenzionale 
Lingua Insegnamento
ITALIANO 



Informazioni aggiuntive

Course Curriculum CFU Length(h)
[70/89]  ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING [89/20 - Ord. 2016]  ELETTRONICA 8 80
[70/89]  ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING [89/30 - Ord. 2016]  INFORMATICA 8 80
[70/89]  ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING [89/56 - Ord. 2016]  ELETTRONICA ON LINE E IN PRESENZA (BLENDED) 8 80
[70/89]  ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING [89/66 - Ord. 2016]  INFORMATICA ON LINE E IN PRESENZA (BLENDED) 8 80

Objectives

The aim of the course is to provide students with basic knowledge used for the realization of digital systems. Starting from the basis of digital electronics and computer science, the student will be able to design simple digital systems. The constant use of the simulator and syntesizer will allow the student to selfcheck the project and to address the practical design with continual references.
Indicator knowledge and understanding
Thanks to its methodological rigor of scientific subjects the student will mature skills and ability of understanding that will allow him to acquire basic knowledge essential for the course of studies.
Indicator ability to apply knowledge and understanding
The teaching approach that provides the theoretical training is accompanied by examples and applications that call for active participation and proactive attitude.
Indicator independent judgment
The study of the circuits will help developing the ability to evaluate the results, select what information is relevant and which approximations are appropriate.
Indicator skills comunicatitive
The development of group exercises requires the student to acquire ability to communicate both the results obtained and the problems encountered.
Indicator ability to learn independently
The use of the simulator and syntetizer allows the student to learn how to selfcheck circuits and understanding the basic mechanism of digital system design.

Prerequisites

The knowledge of the principles taught in the introductory courses of computer science, mathematics, physics.

Contents

Introduction to digital systems. Summary of previous knowledge on logic gates, combinatorial and sequential networks, memories, processors architecture (Lessons: 8 hours).
Implementation of logic gates. Time, delays, waves. Introduction to Verilog-HDL. Delay models in Verilog. Testbench. Simulation of simple combinatorial networks with delay. Synchronous and Asynchronous systems. Setup and hold time in a flip-flop D. Critical path. Maximum clock frequency (Lessons: 10 hours, Lab/Ex: 6 hours).
Control and data-path. Study and HDL coding of a simplified architecture of a microcontrollers processor. Simulation of a simple assembly code. Comparison with a circuit not processor based performing the same task (Lessons: 3 hours, Lab/Ex: 5 hours).
Physical implementation of a digital system: PCB, ASIC, FPGA. Design flow, libraries, components. CLB of a Xilinx-Artix7. Synthesis of a digital system on FPGA. Design, simulation, synthesis of a device for a visualization on the 8 displays of the Nexys-4 Digilent board (Lessons: 3 hours, Lab/Ex: 5 hours).
State machine as controller. Mealys and Moores model and timing. Examples. Labs on de-bouncing, event counter (decimal) and second timer (Lessons: 5 hours, Lab/Ex: 3 hours).
Serial protocols and peripherals communication. Nexys-4 Accelerometer, registers reading and designing of a level (Lessons: 5 hours, Lab/Ex: 6 hours).
Other examples of data-path and control: design of a FIFO using a RAM memory, serial interface of A/D-D/A converters, watch and wake-up timer (Lessons: 5 hours, Lab/Ex: 3 hours).
Performance increase in digital circuits, pipelining. Microcontroller system architecture, bus, peripherals, serial protocols. Comparison between FPGA design and microcontroller based design: design flow, efficiency, costs (Lessons: 5 hours).

Contents

Introduction to digital systems. Summary of previous knowledge on logic gates, combinatorial and sequential networks, memories, processor’s architecture (Lessons: 8 hours).
Implementation of logic gates. Time, delays, waves. Introduction to Verilog-HDL. Delay models in Verilog. Testbench. Simulation of simple combinatorial networks with delay. Synchronous and Asynchronous systems. Setup and hold time in a flip-flop D. Critical path. Maximum clock frequency (Lessons: 10 hours, Lab/Ex: 6 hours).
Control and data-path. Study and HDL coding of a simplified architecture of a microcontroller’s processor. Simulation of a simple assembly code. Comparison with a circuit not processor based performing the same task (Lessons: 3 hours, Lab/Ex: 5 hours).
Physical implementation of a digital system: PCB, ASIC, FPGA. Design flow, libraries, components. CLB of a Xilinx-Artix7. Synthesis of a digital system on FPGA. Design, simulation, synthesis of a device for a visualization on the 8 displays of the Nexys-4 Digilent board (Lessons: 3 hours, Lab/Ex: 5 hours).
State machine as controller. Mealy’s and Moore’s model and timing. Examples. Labs on de-bouncing, event counter (decimal) and second timer (Lessons: 5 hours, Lab/Ex: 3 hours).
Serial protocols and peripherals communication. Nexys-4 Accelerometer, registers reading and designing of a level (Lessons: 5 hours, Lab/Ex: 6 hours).
Other examples of data-path and control: design of a FIFO using a RAM memory, serial interface of A/D-D/A converters, watch and wake-up timer (Lessons: 5 hours, Lab/Ex: 3 hours).
Performance increase in digital circuits, pipelining. Microcontroller system architecture, bus, peripherals, serial protocols. Comparison between FPGA design and microcontroller based design: design flow, efficiency, costs (Lessons: 5 hours).

Teaching Methods

Every week about 5 hours are dedicated to lessons (including simple exercises) other 3 hours are devoted to practice on simulator and synthesizer.

Verification of learning

The assessment of the learning results takes place through a written test which involves the design of a digital system of the same complexity as those of the exercises carried out in class which led to implementations on the FPGA through simulation and synthesis process. Due to the unavailability of the software at the exams, but above all due to the limit of the duration of the test, the complete and functioning solution of the exercise is not required but that of some parts that prove that, with more time and after a normal iterative self-correction process, the student would be able to successfully design the digital device requested. The minimum level of knowledge required to pass the exam is the one able to demonstrate sufficient mastery of the VERILOG language and the organization of a digital system.

Texts

See http://people.unica.it/luigiraffo/didattica/materiale-didattico/progettazione-dei-sistemi-digitali/

More Information

The use of the simulator and synthesizer allows the student to self-check the solutions of the exercises made available on the website.

Questionnaire and social

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